1. Field of the Invention
The present invention relates in general to the process for fabricating CMOS transistors. In particular, the present invention relates to a process for fabricating CMOS transistors having high-voltage metal-gates. More particularly, the present invention relates to a process for fabricating CMOS transistors having heavily-doped source and drain terminals that are precisely formed in symmetry respectively within the lightly-doped source and drain regions, and featuring precisely controlled uniformity of the transistor characteristics for the high-voltage metal-gate CMOS transistors fabricated.
2. Technical Background
Conventional processes for fabricating high-voltage metal-gate CMOS transistors suffer from poor dimensional alignment and symmetry for the fabricated source/drain terminals that are prerequisites for the uniformity of the transistor characteristics for these CMOS transistor devices fabricated. The poor alignment and symmetry characteristics found in the conventional fabrication processes are inherent in the nature of the fabrication process steps employed. Poor alignment and dissymmetry in the source and drain regions of the CMOS transistor result in variations of the electrical characteristics for the CMOS transistors produced in different production batches, as the fabrication process conditions may vary for the alignments involved in the process steps.